1. Field of the Invention
The present invention generally relates to processor-oriented systems with a direct mapped I/O architecture.
2. Description of the Related Art
Conventional computer systems provide an I/O address space, which can be accessed with machine instructions such as IN and OUT via addresses in the I/O address space, usually referred to as xe2x80x9cports.xe2x80x9d The standard PC architecture supports an I/O address space of 64K ports using the addresses 0000h to FFFFh. The ports in I/O address space are mostly used for addressing registers in peripheral devices. The IN and OUT instructions transfer data between a processor and the peripheral device registers. When a conventional computer system performs an I/O mapped input or output, the registers have been located in the I/O address space, in contrast to memory mapped I/O, where the peripheral device registers are located in the conventional memory address space. When an I/O mapped input or output is to be performed, a processor usually sends an address signal to an address decoder which decodes the address and then addresses the proper port.
The IBM PC/AT architecture defined a set of ports which has become an industry standard. These ports provide standard I/O addresses for such devices as Direct Memory Access (DMA) controllers, keyboards, interrupt controllers, programmable interval timers and serial I/O. In modem microprocessors, many of these devices are often integrated into the processor chipset. However, not all addresses in the 64K I/O address space are assigned by the PC/AT standard. I/O to unassigned ports is typically sent to a bus controller where either some device will respond to the I/O attempt or an error will be generated.
Even for computer systems providing a peripheral bus such as a Peripheral Component Interconnect (PCI) bus, ports have not typically been directly mapped to the peripheral bus. New devices built for such a peripheral bus therefore have been indirectly mapped, at a cost of performance. While I/O to a direct mapped device is sent directly one or more of the ports assigned to the direct mapped device with an I/O instruction, I/O to an indirectly mapped device has typically been performed by sending both the address and the data to one or more ports assigned to the device or to a bus controller. For example, PCI bus devices are typically indirectly mapped using a pair of I/O ports at 0CF8h and 0CFCh. To write a PCI device register, systems load an address in one port, and then data to the other port.
Many conventional computer systems have provided integrated I/O devices to which standard ports are permanently assigned. In conventional computer systems, I/O to unassigned ports has been sent to a peripheral bus, typically an Industry Standard Architecture (ISA) bus, for decoding.
Briefly, a processor-oriented system provides a flexible way to send accesses to ports not assigned to integrated I/O devices to one of two busses, as controlled by a programmable address decoder. The programmable address decoder includes a programmable address router to route I/O addresses to the two busses under the control of a programmable switch. When the programmable switch provides a first predetermined value, the programmable address router routes I/O addresses to the first bus. When the programmable switch provides a second predetermined value, the programmable address router routes I/O addresses to the second bus. One advantage of such a mechanism is that new devices built for a second bus can be directly mapped to the relevant ports, avoiding performance penalties.
Another aspect of such a system allows disabling integrated I/O devices coupled to the first bus and allowing I/O for the associated ports to be passed to other devices on the bus by the bus controller. In one aspect, the first bus may have an internal and an external portion. One advantage of this aspect is that this allows connection of external devices such as a standard Super I/O chip, in place of integrated I/O devices.